Logic verification engineer

Требования:
• ph.D. Or m.S. In electronics engineering, computer science, mathematics, physics, or related areas
• practical experience on rtl function verification
• verification language experience (specman e, vera, systemverilog)
• hardware description language (verilog, vhdl)
• basic knowledge on amba based soc architecture
• scripting skill with csh, sh, perl, tcl, makefile, etc.
• assertion and formal verification experience
• knowledge on standard interface protocols (ahb, axi, i2c, i2s, uart, etc.)
• knowledge on standard verification methodology (erm, ovm, vmm)


Должностные обязанности:
Job summary • developing verification methodology and supporting verification activities in design team
• helping testbench development and consulting on verification planning
• developing automated design/verification solutions (in-house tools and scripts)
• developing reusable verification ip
• evaluating new verification tools
• technical support and management of verification eda tools
responsibility/duty • research and development on verification methodologies
• improving verification efficiency with automation
• qualification on verification quality of internal reusable ips
• verification tool evaluation and management